1. Field of the Invention
The present invention relates to a monolithic ceramic electronic component and a method for manufacturing the monolithic ceramic electronic component. In particular, the present invention relates to a monolithic ceramic electronic component including a ceramic body having inner conductors and via conductors, and to a method for manufacturing the monolithic ceramic electronic component.
2. Description of the Related Art
Regarding a power supply circuit, when a voltage fluctuation of a power line is increased due to an impedance of the power line or ground, operation of circuits driven by the power supply circuit may become unstable, the circuits may interfere with each other via the power supply circuit, or an oscillation may occur. To prevent this, a decoupling capacitor is usually connected between the power line and ground. The decoupling capacitor serves to reduce the impedance between the power line and ground, and to suppress fluctuation of a power supply voltage and interference between the circuits.
In recent years, high-speed signals have been used in communication equipment, such as mobile phones, and information processing equipment, such as personal computers, in order to handle a large amount of information, and clock frequencies of ICs used in such equipment have increased. Therefore, noise including a lot of harmonic content is easily generated, which necessitates more effective decoupling for an IC power supply circuit.
Using a decoupling capacitor with an excellent impedance frequency characteristic is effective for increasing a decoupling effect. A monolithic ceramic capacitor is an example of such a decoupling capacitor. Because a monolithic ceramic capacitor has a low ESL (equivalent series inductance), a monolithic ceramic capacitor has an excellent noise absorption characteristic across a frequency band wider than that of an electrolytic capacitor.
To increase a decoupling effect, disposing a decoupling capacitor as near as possible to power pins of an IC is also effective. This is because, when the distance between power pins of an IC and the decoupling capacitor is short, parasitic inductance of lines therebetween is low and the impedance of a power line becomes low.
FIGS. 16 to 18 show a monolithic ceramic capacitor 1 disclosed in Japanese Unexamined Patent Application Publication No. 2001-203125, which is used here as an example of a conventional monolithic ceramic electronic component that is a related art. More specifically, FIG. 16 is a sectional front view of the monolithic ceramic capacitor 1, FIG. 17 is a sectional plan view taken along line XVII-XVII of FIG. 16, and FIG. 18 is a sectional plan view taken along line XVIII-XVIII of FIG. 16.
The monolithic ceramic capacitor 1 includes a ceramic body 3 in which a plurality of ceramic layers 2 are stacked. First and second inner conductors 4 and 5 are disposed in the ceramic body 3 in such a manner that the first and second inner conductors 4 and 5 extend parallel to interfaces between the ceramic layers 2. The first and second inner conductors 4 and 5 are provided in pairs so that the first and second inner conductors are disposed opposite each other with a specific one of the ceramic layers 2 therebetween.
On a main surface of the ceramic body 3, first and second outer terminal electrodes 6 and 7 are alternately formed in a matrix pattern. Likewise, on the other main surface of the ceramic body 3, the first and second outer terminal electrodes 6 and 7 are alternately formed in a matrix pattern.
First via conductors 8 and second via conductors 9 are formed in the ceramic body 3 in such a manner that the first and second via conductors 8 and 9 extend in the stack direction of the ceramic layers 2. The first via conductors 8 are electrically connected to the first inner conductors 4 and the first outer terminal electrodes 6. The first via conductors 8 are electrically isolated from the second inner conductors 5. The second via conductors 9 are electrically connected to the second inner conductors 5 and the second outer terminal electrodes 7. The second via conductors 9 are electrically isolated from the first inner conductors 4.
The monolithic ceramic capacitor 1 has a low ESL because the first and second via conductors 8 and 9 are alternately disposed so that magnetic fields generated around the first and second via conductors 8 and 9 cancel each other out. Moreover, because the first and second outer terminal electrodes 6 and 7 are formed on the upper and lower surfaces of the ceramic body 3, the monolithic ceramic capacitor 1 can be easily mounted on the bottom surface of an IC (not shown), and the distance between the monolithic ceramic capacitor 1 and the IC can be made short.
As described above, in the monolithic ceramic capacitor 1, the first via conductors 8, which have a potential different from that of the second inner conductors 5, are electrically isolated from the second inner conductors 5, and the second via conductors 9, which have a potential different from that of the first inner conductors 4, are electrically isolated from the first inner conductors 4. For this isolation, the first inner conductors 4 have openings 10 through which the second via conductors 9, which have a potential different from that of the first inner conductors 4, extend. The second inner conductors 5 have openings 11 through which first via conductors 8, which have a potential different from that of the second inner conductors 5, extend. The first and second via conductors 8 and 9 respectively extend through the centers of the openings 11 and 10.
The first and second inner conductors 4 and 5 are formed by printing an electrically conductive paste on ceramic green sheets that will become the ceramic layers 2 by a printing method such as screen printing. However, as shown in FIG. 19, when the electrically conductive paste 12 is printed, a smear 14 may be generated in the opening 10 or 11 of the first or second inner conductor 4 or 5 at a side of the opening near to a position from which printing is started in the printing direction 13 by the printing method. If the smear 14 is large, the first or second inner conductor 4 or 5 may contact the first or second via conductor 9 or 8 having a different potential and cause a short-circuit.
As described above, screen printing is an example of a printing method that may generate a smear. As long as an electrically conductive paste is used, other printing methods, such as a gravure printing method, may have a similar problem.